A DRAM has advantages of being low in cost, simple in structure, and high in density within unit area, and is thus commonly applied in various consumer electronic products, e.g., a master memory of a personal computer. An electronic device usually reads data from or writes data to a DRAM via a memory controller. For example, to read data from a DRAM, a memory controller first sends an ACTIVE command, specifying a predetermined row address, for asking the DRAM to load a content of the predetermined row to a memory bank. The memory controller then sends a READ command, specifying a memory bank address and a column address, for acquiring the data temporarily stored in the predetermined column of the predetermined memory bank.
To optimize operation performance, in general, the memory controller consecutively sends a plurality of commands to the DRAM. However, noise interference resulted from the differences between the commands on signal lines are not considered in the prior memory controller when sending the commands to the DRAM. For example, supposing that the memory controller consecutively sends two read commands to the DRAM, with address contents of the two commands respectively being hexadecimal 0x0000 and 0xffff. Therefore, when the memory controller switches a signal at its address output end from 0x0000 to 0xffff, noises occur at signal lines for transmitting the address content due to 16 concurrent toggles. The greater the noise is, the more severe interference is imposed on a content of an original signal, and even cause the DRAM at the other end of the signal lines to misjudge contents of the commands.
Despite the trend of increasing both operation efficiency and data amount of electronic devices, the above interference becomes more drastic along with increase of clock speed and number of signal lines. The interference may be lowered by adopting a multi-layer printed circuit board, which however significantly increases overall hardware cost of the electronic device, and is thus an unsatisfactory solution.